In a multi-level Flash memory unit the pages can be separated by n-levels, corresponding to log 2(n) number of bits stored per cell.
FIG. 1 demonstrates eight equally spaced lobes 11-18 that represent eight logic levels per cell. These lobes represent a desired voltage level distribution of 3 bits-per-cell (bpc) flash memory page.
FIG. 1 also illustrates a most significant bit (MSB) read threshold 25, two center significant bit (CSB) read thresholds 23 and 27 and four least significant bit (LSB) read thresholds 22, 24, 26 and 28.
To read an MSB page, a single threshold comparison can be performed (with MSB read threshold 25). To read a CSB page, two read thresholds can be used (CSB read thresholds 23 and 27) to determine the bit value of every CSB associated cell. For LSB pages the bit-values may be determined by using the four LSB read thresholds 22, 24, 26 and 28.
In FIG. 1 the voltage level distributions per level (represented by the lobes) are non-overlapping, however this is only schematic, and in practical cases the distributions may overlap.
Overlapping may be programmed to obtain high programming speed, or can be due to the retention effect. For floating gate devices, an “old” page, may introduce greater overlap between lobes than a new page, since after many program/erase (P/E) cycles there may be an accumulated trap charge, which can be de-trapped over time. After a long duration, every lobe may have a larger standard deviation and may have a different mean location. These are just two examples for overlapping distributions. There may be many more, such as read disturbs, programming disturbs, etc.
The overlap of the lobes distribution induces page read errors. The greater the overlap, the higher can be the error probability. For a Gaussian distribution per lobe, the probability of error for a specific lobe, may be given by using the complementary error function,
            P      e        ⁡          (              n        ,                  x          th                    )        =            1      2        ⁢          erfc      ⁡              (                                                                        x                th                            -                              μ                n                                                          σ                )                            σ—nth lobe std        μn—nth lobe mean voltage        n—lobe index (0, . . . , 7 for 3 bpc)where erfc is the conventional complementary error function        
      erfc    ⁡          (      z      )        =            1                        2          ⁢          π                      ⁢                  ∫        z        ∞            ⁢                        ⅇ                                    -                              t                2                                      /            2                          ⁢                                  ⁢                  ⅆ          t                    
The error probability around a certain read threshold may be the sum of error probabilities for two neighboring lobes. For the example of 3-bits-per-cell (where there are 8 lobes), the single threshold error probability can be given by
            P              e        ,        TH              ⁡          (              n        ,                  x          th                    )        =            1      8        ⁢          (                                    P            e                    ⁡                      (                          n              ,                              x                th                                      )                          +                              P            e                    ⁡                      (                                          n                +                1                            ,                              x                th                                      )                              )      
For the different page types (MSB, CSB, LSB), the error probability depends on the number of read thresholds. For low error probabilities, the bit-type bit error rate for 3 bpc can be approximated as depicted by FIG. 2,Pe,MSB=Pe,TH(3,xth,3)Pe,CSB=Pe,TH(1,xth,1)+Pe,TH(5,xth,5)Pe,CSB=Pe,TH(0,xth,0)+Pe,TH(2,xth,2)+Pe,TH(4,xth,4)+Pe,TH(6,xth,6)
In a multi-level Flash memory unit the pages may be separated by n-levels, corresponding to log2(n) number of bits stored per cell.
FIG. 2 depicts eight equally spaced lobes 31-38 that represent eight logic levels per cell. These lobes overlap (in contrary to non-overlapping lobes 11-18 of FIG. 1) and represent a voltage level distribution of 3 bits per cell flash memory page. FIG. 2 also illustrates MSB read threshold 45, two CSB read thresholds 43 and 47, and four LSB read thresholds 42, 44, 46 and 48.
Error probability can change as a function of lobe spacing, and read thresholds location. In prior-art applications, the lobe spacing can be usually designed to be equal, such that the same probability of error may be obtained for every read threshold. Denote the probability of error per read threshold as pe. Then, the bit-error probability of MSB pages may be Pe,MSB=pe, for CSB can be approximately Pe,CSB=2pe, and the LSB can be approximately Pe,LSB=4pe.